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Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
This is family of 4194304 - word by 64 - bit dynamic RAM module. This consists of four industry standard 4Mx16 dynamic RAMs in TSOP and one industry EEPROM in TSSOP. The mounting of TSOP on a card edge dual in line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module,suitable for easy interchange of addition of modules.
ADDRESS
Part No. MH4V64AXJJ MH4V644AXJJ Row Add. Col Add. A0~A12 A0~A11 Refresh
/RAS only Ref,Normal R/W A0~A8 CBR Ref,Hidden Ref
Refresh Cycle 8192/64ms 4096/64ms 4096/64ms
A0~A9
/RAS only Ref,Normal R/W CBR Ref,Hidden Ref
APPLICATION
Main memory unit for computer,Microcomputer memory,Refresh memory for CRT.
*:Applicable to self refresh version(MH4V64/644AXJJ-5S,-6S) only
FEATURES
RAS CAS Address OE access access access access Cycle time time time time time (min.ns) (max.ns) (max.ns) (max.ns) (max.ns) MH4V64AXJJ-5,5S MH4V64AXJJ-6,6S MH4V644AXJJ-5,5S MH4V644AXJJ-6,6S 50 60 50 60 13 15 13 15 25 30 25 30 13 15 13 15 90 110 90 110
single 3.3V 0.3V supply Low stand-by power dissipation 7.2mW- - - - - - - - - LVCMOS input level operating power dissipation MH4V64AXJJ-5,5S - - - - - 1584 mW(max.) MH4V64AXJJ-6,6S - - - - - 1440mW(max.) MH4V644AXJJ-5,5S - - - - 2016 mW(max.) MH4V644AXJJ-6,6S - - - - 1872 mW(max.) Self refresh capability* Self refresh current - - - - 1600 uA(max.) All input, output LVTTL compatible and low capacitance Utilizes industry standard 4Mx16 RAMs in TSOP and industry standard EEPROM in TSSOP. Includes decoupling capacitor(0.22uFx4) Fast page mode , Read-modify-write, CAS before RAS refresh,Hidden refresh capabilities. Early-write mode,OE to control output buffer impedance.
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 1 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
PIN Number Front side Pin Name PIN Number Back side Pin Name PIN Number Front side Pin Name PIN Number Back side Pin Name
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss /CAS0 /CAS1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss Reserved Reserved RFU Vcc RFU /WE /RAS0 NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss /CAS4 /CAS5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss Reserved Reserved FRU Vcc RFU RFU RFU RFU
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
/OE Vss Reserved Reserved Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc /CAS2 /CAS3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
RFU Vss Reserved Reserved Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 A11 Vss A12/NC(note) NC Vcc /CAS6 /CAS7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
RFU:Reserved Future Use NC,RFU,Reserved: NO CONNECTION
Note:A12 ... MH4V64AXJJ , NC ... MH4V644AXJJ
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 2 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram Address /OE /WE /RAS0 /CAS0 /LCAS /RAS /WE /OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D1 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /CAS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /CAS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 SERIAL PD Vcc
C1~C4
/CAS4 /LCAS /RAS /WE /OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 /UCAS I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 D2
D3
D0 to D3 D0 to D3
SCL
A0 A1 A2
SDA
Vss
Vss
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 3 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5,-6)
Bytes 1 2 3 4 5 6 7 8 9
Function described Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly RAS# access time of this assembly -5 -6
SPD entry data 256 Bytes FPM DRAM A0-A12 A0-A8 1bank x64 0 3.3V LVTTL 50ns 60ns 13ns 15ns non parity N/R(15.625uS) x16 N/A open open Rev 1 Check sum for -5 Check sum for -6
SPD DATA entry(Hex) 08 01 0D 09 01 40 00 02 32 3C 0D 0F 00 00 10 00 00 00 01 32 3E 1CFFFFFFFFFFFFFF 01 02 03 04 4D483456363441584A4A2D352D35202020202020 4D483456363441584A4A2D362D36202020202020 rrrr yy/ww ssssssss 00 00 00
10
CAS# access time of this assembly
-5 -6
11 12 13 14 15-31 32-61 62 63
DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type DRAM width,Primary DRAM Error Checking DRAM data width Reserved for future offerings Superset Memory type(may be used in future) SPD Data Revision Code Checksum for bytes 0-62
64-71 72
Manufacturers JEDEC ID code per JEP-106 Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany
73-90
Manufacturer's Part Number
MH4V64AXJJ-5 MH4V64AXJJ-6
91-92 93-94 95-98 99-125 126-127 128-255
Revision Code Manufacturing date Assembly Serial Number Manufacturer Specific Data Reserved Open User Free-Form area not defined
PCB revision year/week code serial number open open open
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 4 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V64AXJJ-5S,-6S)
Bytes 1 2 3 4 5 6 7 8 9
Function described Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly RAS# access time of this assembly -5S -6S
SPD entry data 256 Bytes FPM DRAM A0-A12 A0-A8 1bank x64 0 3.3V LVTTL 50ns 60ns 13ns 15ns non parity S/R(15.625uS) x16 N/A open open Rev 1 Check sum for -5 Check sum for -6
SPD DATA entry(Hex) 08 01 0D 09 01 40 00 02 32 3C 0D 0F 00 80 10 00 00 00 01 B2 BE 1CFFFFFFFFFFFFFF 01 02 03 04
10
CAS# access time of this assembly
-5S -6S
11 12 13 14 15-31 32-61 62 63
DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type DRAM width,Primary DRAM Error Checking DRAM data width Reserved for future offerings Superset Memory type(may be used in future) SPD Data Revision Code Checksum for bytes 0-62
64-71 72
Manufacturers JEDEC ID code per JEP-106 Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany
73-90
Manufacturer's Part Number
MH4V64AXJJ-5S 4D483456363441584A4A2D355335532020202020 MH4V64AXJJ-6S 4D483456363441584A4A2D365336532020202020
91-92 93-94 95-98 99-125 126-127 128-255
Revision Code Manufacturing date Assembly Serial Number Manufacturer Specific Data Reserved Open User Free-Form area not defined
PCB revision year/week code serial number open open open
rrrr yy/ww ssssssss 00 00 00
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 5 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5,-6)
Bytes 0 1 2 3 4 5 6 7 8 9 Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly RAS# access time of this assembly -5 -6 10 CAS# access time of this assembly -5 -6 11 12 13 14 15-31 32-61 62 63 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type DRAM width,Primary DRAM Error Checking DRAM data width Reserved for future offerings Superset Memory type(may be used in future) SPD Data Revision Code Checksum for bytes 0-62 SPD entry data 128 256 Bytes FPM DRAM A0-A11 A0-A9 1bank x64 0 3.3V LVTTL 50ns 60ns 13ns 15ns non parity N/R(15.625uS) x16 N/A open open Rev 1 Check sum for -5 Check sum for -6 64-71 72 Manufacturers JEDEC ID code per JEP-106 Manufacturing location MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany 73-90 Manufacturer's Part Number SPD DATA entry(Hex) 80 08 01 0C 0A 01 40 00 02 32 3C 0D 0F 00 00 10 00 00 00 01 32 3E 1CFFFFFFFFFFFFFF 01 02 03 04
MH4V644AXJJ-5 4D48345636343441584A4A2D352D352020202020 MH4V644AXJJ-6 4D48345636343441584A4A2D362D362020202020
91-92 93-94 95-98 99-125 126-127 128-255
Revision Code Manufacturing date Assembly Serial Number Manufacturer Specific Data Reserved Open User Free-Form area not defined
PCB revision year/week code serial number open open open
rrrr yy/ww ssssssss 00 00 00
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 6 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Serial Presence Detece TABLE (MH4V644AXJJ-5S,-6S)
Bytes 0 1 2 3 4 5 6 7 8 9
Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly RAS# access time of this assembly -5S -6S
SPD entry data 128 256 Bytes FPM DRAM A0-A11 A0-A9 1bank x64 0 3.3V LVTTL 50ns 60ns 13ns 15ns non parity S/R(15.625uS) x16 N/A open open Rev 1 Check sum for -5S Check sum for -6S
SPD DATA entry(Hex) 80 08 01 0C 0A 01 40 00 02 32 3C 0D 0F 00 80 10 00 00 00 01 B2 BE 1CFFFFFFFFFFFFFF 01 02 03 04
10
CAS# access time of this assembly
-5S -6S
11 12 13 14 15-31 32-61 62 63
DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type DRAM width,Primary DRAM Error Checking DRAM data width Reserved for future offerings Superset Memory type(may be used in future) SPD Data Revision Code Checksum for bytes 0-62
64-71 72
Manufacturers JEDEC ID code per JEP-106 Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany
73-90
Manufacturer's Part Number
MH4V644AXJJ-5S 4D48345636343441584A4A2D3553355320202020 MH4V644AXJJ-6S 4D48345636343441584A4A2D3653365320202020
91-92 93-94 95-98 99-125 126-127 128-255
Revision Code Manufacturing date Assembly Serial Number Manufacturer Specific Data Reserved Open User Free-Form area not defined
PCB revision year/week code serial number open open open
rrrr yy/ww ssssssss 00 00 00
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 7 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
a number of other functions, e.g., Fast page mode, /RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
FUNCTION
The MH4V64/644AXJJ provide, in addition to normal read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Inputs Operation Read Write (Early write) Write (Delayed write) Read-modify-write /RAS-only refresh Hidden refresh /CAS before /RAS refresh Standby Self refresh * /RAS ACT ACT ACT ACT ACT ACT ACT NAC ACT /CAS ACT ACT ACT ACT NAC ACT ACT DNC ACT /W NAC ACT ACT ACT DNC NAC NAC DNC NAC Input/Output Refresh Remark Row Column /OE address address Input Output ACT APD APD OPN VLD YES Fast page DNC APD APD VLD OPN YES mode DNC APD APD VLD IVD YES identical ACT APD APD VLD VLD YES DNC APD DNC DNC OPN YES ACT APD DNC OPN VLD YES DNC DNC DNC DNC OPN YES DNC DNC DNC DNC OPN NO DNC DNC DNC DNC OPN YES
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open *MH4V64/644AXJJ-5S,-6S only
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 8 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Conditions With respect to Vss
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature (SOJ) Ratings -0.5~4.6 -0.5~4.6 -0.5~4.6 50 4 0~ 70 -40~ 100 Unit V V V mA W C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs
(Ta=0~ 70C, unless otherwise noted) (Note 1)
Min 3.0 0 2.0 **-0.3
Limits Nom 3.3 0
Max 3.6 0 Vcc+0.3 0.8
Unit V V V V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS [MH4V64AXJJ]
Symbol VOH VOL IOZ II Parameter
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0VVOUT3.6V 0VVIN3.6V, Other input pins=0V /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CASVcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min.,/WVcc-0.2 output open
High-level output voltage Low-level output voltage Off-state output current Input current Average supply -5,-5S ICC1 (AV) current from Vcc operating (Note 3,4,5) -6,-6S ICC2 Supply current from Vcc , stand-by
Min 2.4 0 -10 -40
Limits Typ Max Vcc 0.4 10 40 440 400 4 2 400 360 560
Unit V V uA uA mA
mA mA
Average supply current -5,-5S ICC4(AV) from Vcc Fast-Page-Mode (Note 3,4,5) -6,-6S
Average supply current -5,-5S from Vcc ICC6(AV) /CAS before /RAS refresh mode (Note 3,5) -6,-6S
mA 520
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 9 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS [MH4V644AXJJ]
Symbol VOH VOL IOZ II Parameter
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0VVOUT3.6V 0VVIN3.6V, Other input pins=0V /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CASVcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min.,/WVcc-0.2 output open /CAS before /RAS refresh cycling tRC=min. output open
High-level output voltage Low-level output voltage Off-state output current Input current Average supply -5,-5S ICC1 (AV) current from Vcc operating (Note 3,4,5) -6,-6S ICC2 Supply current from Vcc , stand-by
Min 2.4 0 -10 -40
Limits Typ Max Vcc 0.4 10 40 560 520 4 2 420 380 560
Unit V V uA uA mA
mA mA
Average supply current -5,-5S ICC4(AV) from Vcc Fast-Page-Mode (Note 3,4,5) -6,-6S
Average supply current -5,-5S from Vcc ICC6(AV) /CAS before /RAS refresh (Note 3,5) -6,-6S mode
mA 520
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH
CAPACITANCE
Symbol CI (A) CI C(CAS) C(DQ) C(SDA) C(SCL)
(Ta = 0~70C, Vcc = 3.3V0.3V, Vss = 0V, unless otherwise noted)
Parameter Input capacitance, address inputs
Input capacitance, clock inputs except CAS
Test conditions VI=Vss f=1MHZ Vi=25mVrms
Min
Input capacitance, CAS Input/Output capacitance,DATA Input/Output capacitance,SDA Input capacitance, SCL
Limits Typ Max 40 45 25 25 12 12
Unit pF pF pF pF pF pF
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 10 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
otherwise noted , see notes 6,13,14)
SWITCHING CHARACTERISTICS (Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless
Limits Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Parameter (Note 7,8) Access time from /CAS (Note 7,9) Access time from /RAS (Note 7,10) Column address access time (Note 7,11) Access time from /CAS precharge (Note 7) Access time from /OE Output low impedance time from /CAS low (Note 7) (Note 12) Output disable time after /CAS high (Note 12) Output disable time after /OE high -5,-5S Min Max 13 50 25 30 13 5 13 0 13 0
-6,-6S Min Max 15 60 30 35 15 5 15 0 15 0
Unit ns ns ns ns ns ns ns ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS clock such as /RAS-Only refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL). 8: Assumes that tRCDtRCD(max), tASCtASC(max) and tCPtCP(max). 9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRADtRAD(max) and tASCtASC(max). 11: Assumes that tCPtCP(max) and tASCtASC(max). 12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT I 10uAI) and is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT
Parameter Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /CAS high to data Delay time, /OE high to data Transition time
(Note15)
(Note16) (Note17)
(Note18) (Note18) (Note19) (Note19) (Note20)
Limits -5,-5S -6,-6S Min Max Min Max 64 64 30 40 18 37 20 45 10 5 0 0 10 10 13 15 25 30 0 0 5 10 0 0 8 10 13 15 0 0 0 0 13 15 13 15 1 50 1 50
Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics are 2.0V and 0.8V respectively. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min)=tRAH(min)+2tT+tASC(min) . 16: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
( 11 / 25 )
26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Limits -5,-5S -6,-6S Min Max Min Max 90 110 50 10000 60 10000 13 10000 15 10000 50 60 13 15 0 0 (Note 21) 0 0 (Note 21) 10 10 25 30 13 15 13 15
Read and Refresh Cycles
Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Parameter Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time /CAS hold time after /OE low /RAS hold time after /OE low Unit ns ns ns ns ns ns ns ns ns ns ns
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low (Note 23) Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low /OE hold time after /W low Limits -5,-5S -6,-6S Min Max Min Max 90 110 50 10000 60 10000 13 10000 15 10000 50 60 13 15 0 0 10 10 13 15 13 15 10 10 0 0 10 10 13 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Parameter Limits -5,-5S -6,-6S Min Max Min Max 130 150 85 10000 95 10000 50 10000 50 10000 85 95 50 50 0 0 30 30 65 75 40 45 15 15 15 15 10 10 0 0 10 10 10 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Read-Write and Read-Modify-Write Cycles
Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH
Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /W low Date hold time after /W low /OE hold time after /W low
(Note22)
(Note23) (Note23) (Note23)
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWDtCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
/RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to /W low
(Note25) (Note26) (Note23)
Limits -5,-5S -6,-6S Min Max Min Max 35 40 70 75 85 125000 100 100000 5 10 10 15 30 35 30 35
Unit ns ns ns ns ns ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of /CAS input are performed. 26: tCP(max) is specified as a reference point only.If tCPtCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Limits -5,-5S -6,-6S Min Max Min Max 5 5 10 10 10 10 10 10 Unit ns ns ns ns
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.
MIT-DS-0072-0.5
MITSUBISHI ELECTRIC
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26/Feb./1997
Preliminary
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item,line -5S / -6S. The other characteristics and requirements then below are same as normal device.
ELECTRIC CHARACTERISTICS (Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless
Symbol Parameter Test conditions
otherwise noted) (Note 2)
Min
Limits Typ Max 1600
Unit A
/RAS=/CAS<0.2V Average supply current ICC9(AV)* from Vcc Self-Refresh mode -5S,-6S /OE=/W=A0~A12(A11)=Vcc-0.2V or 0.2V output=Vcc-0.2V,0.2V or open (Note 6)
TIMING REQUIREMENTS
Symbol tRASS tRPS tCHS
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits -5S Min Max Min 100 110 - 50 100 90 - 50 -6S Max us ns ns
Parameter CBR Self Refresh RAS low pulse width CBR Self Refresh RAS high precharge time CBR Self Refresh RAS hold time
Unit
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 64 ms and tSN 64 ms. tNS Self refresh period
DISTRIBUTED REFRESH < 64 ms > DISTRIBUTED REFRESH < 64 ms >
tSN
(2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS 16ms and tSN 16 ms. tSN tNS Self refresh period
BURST REFRESH < 64 ms > BURST REFRESH < 64 ms >
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MITSUBISHI ELECTRIC
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
(Note 28)
Timing Diagrams Read Cycle
tRC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR VIH Address VIL tRRH tRCS VIH W VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
tRP
tRCD
tRSH tCAS
tRPC
tCRP
tRAD tRAH tASC tCAH
COLUMN ADDRESS
tRAL tCPN
tASR
ROW ADDRESS
ROW ADDRESS
tRCH
tCDD
DQ (INPUTS)
tOFF
VOH Hi-Z VOL tRAC tDZO VIH tOEA tOCH tOEZ tODD
DATA VALID
Hi-Z
OE
VIL
tORH
Note 28
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output.
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC tCRP
CAS
Address
ROW ADDRESS
tWCS W VIH VIL tDS
DQ (INPUTS)
tWCH
tDH
VIH VIL
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
tRCD
tRSH tCAS
tRPC tCRP
Address
VIH VIL
ROW ADDRESS
tCWL tRCS VIH W VIL tWCH tDZC
DQ (INPUTS)
tRWL tWP
tDS Hi-Z tCLZ
tDH
DATA VALID
VIH VIL
DQ (OUTPUTS)
VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z
OE
VIH VIL
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
Address
VIH VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS tDZC
DQ (INPUTS)
tDH
VIH VIL tCAC tAA tCLZ
Hi-Z
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID
Hi-Z tODD tOEZ tOEH
OE
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP VIH RAS VIL tCSR tRAS tRAS
tRC tRP
tRPC VIH CAS VIL
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tCPN tASR Address VIH VIL tRCH tRSR VIH W VIL tRHR tRSR tRHR tRCS
ROW ADDRESS COLUMN ADDRESS
DQ (INPUTS)
VIH VIL tOFF
DQ (OUTPUTS)
VOH VOL tOEZ VIH
Hi-Z
OE
VIL
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tRAD tASR VIH Address VIL tRCS tRAL VIH W VIL tDZC tRRH tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIL tOEA tORH tOEZ tODD
DATA VALID
tOFF
DQ (OUTPUTS)
VOH Hi-Z
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH VIL tRAL tRCS VIH W VIL tDZC tDZC tDZC tRCH tRCS tRCH tRCS tRAH tASC tCAH
COLUMN-1
tRP
tPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
tCPRH tASC tCAH tASC tCAH tASR
ROW ADDRESS
Address
ROW ADDRESS
COLUMN-2
COLUMN-3
tRRH
tRCH
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ tOFF tAA tCLZ
DATA VALID-1 DATA VALID-2
Hi-Z tCAC tOFF tCAC tAA tCLZ
DATA VALID-3
tOFF
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
OE
VIH tDZO tODD tODD tDZO tORH tODD
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
Address
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS VIH W VIL tDS
DQ (INPUTS)
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
DATA VALID-1
tDS
tDH
tDS
tDH
DATA VALID-3
VIH VIL
DATA VALID-2
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tRCD tCAS tCP tRSH tPC tCAS
tRP
tASR
ROW ADDRESS
Address
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS VIH W VIL tWCH tDZC VIH Hi-Z VIL tDS
tCWL tWP
tPCS tWP
tWCH tDH
DATA VALID-1
tDZC tDS Hi-Z
tDH
DATA VALID-2
DQ (INPUTS)
tCLZ
DQ (OUTPUTS)
tCLZ Hi-Z tOEZ tODD tDZO tOEZ tODD tOEH Hi-Z
VOH Hi-Z VOL tDZO VIH
OE VIL
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP CAS tPRWC tCAS
tRP
RAS
tRWL
tASR
ROW ADDRESS
VIH Address VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH VIL tRWD tDZC
DQ (INPUTS)
tAWD tCWL tWP tRCS tCWD tWP
tCWD
W
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
VIH VIL Hi-Z tCAC tAA tCLZ
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID-1
Hi-Z tODD tOEZ tDZO tOEA tCPA
DATA VALID-1
Hi-Z tODD tOEZ tOEH
OE
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
Outline
67.6
3.63MAX
20
3.3 3.7
23.2 29 23.2
4.6
32.8 32.8
25.40
1.00
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